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Sumit Diware

I am an Assistant Professor in the Electronics and Communication Engineering (ECE) Department at Indian Institute of Technology (IIT) Roorkee.

My research focuses on AI-oriented hardware design, where I explore how emerging computing paradigms and memory technologies can be leveraged to shape the next-generation AI hardware. Under this scope, I currently work on hardware-algorithm co-design and system-on-chip architectures for memristor-based computation-in-memory.

I obtained my Ph.D. in Computer Engineering from Delft University of Technology (TU Delft), Netherlands. For my doctoral work, I received European Design and Automation Association (EDAA) Outstanding Dissertation Award at DATE-2025 conference. Before that, I completed M.Tech. in VLSI Design Tools and Technology from IIT Delhi with sponsorship from Qualcomm.

Open Positions

Ph.D. student positions are avaiable for Autumn 2026 semester. Further details for prospective students are provided in Join Us!

Information about the previous rounds of IIT Roorkee Ph.D. admission process can be found here.

Other opportunities (Bachelor's, Master's, internship, RA, post-doc, etc.) are currently unavailable, and will be updated in due time.

Overview

Artificial intelligence (AI) execution on end-user devices instead of cloud servers is known as edge-AI. This approach offers several key benefits like lower latency, reduced network costs, data privacy, and better reliability. However, edge devices have very limited resources such as energy, area, compute capability, etc. As a result, traditional computing architectures and memory technologies struggle to run AI efficiently at the edge. Hence, we need to explore new computing architectures and memory technologies to build AI hardware for edge platforms.

My research explores emerging computing architectures & memory technologies to deploy AI workloads effectively on edge devices.

Current Research

I am currently working on the following broad research themes:

  • Specialized Hardware Architectures for Edge-AI
    Design energy-efficient, scalable, and robust edge hardware for various target AI applications e.g. NLP.
  • Advanced Neuromorphic Hardware Architectures
    Design next-gen AI hardware features like ultra energy-efficient spiking computation, adaptive on-chip learning, etc.
  • System-Level Frameworks for AI Hardware Design
    Develop design tools to facilitate effective hardware development and/or workload deployment on edge-AI.

Under the above themes, I primarily focus on Computation-In-Memory (CIM) using Memristor Device Technologies.

I also occasionally explore fully-digital systems in this context whenever a promising opportunity arises.

Explore More

Here is some (older) literature that provides computation-in-memory basics: CIM-survey, CIM-architecture, Memristor-devices

To know more about my research work, please check out my publications and doctoral thesis.

Some of my selected publications are listed below. The complete publication list is available here.

  • [UNDER-REVIEW]
    Detection of Read-disturb Effects in RRAM-based Computation-In-Memory Architectures for Neural Networks
    M. A. Yaldagard, A. Bende, S. Diware, V. Rana, S. Hamdioui, and R. Bishnoi
    IEEE Transactions on Circuits and Systems I (TCAS-I), 2026
  • [DATE'25]
    Adaptive Multi-Threshold Encoding for Energy-Efficient ECG Classification Architecture using Spiking Neural Network
    S. Diware, Y. Dong, M. A. Yaldagard, S. Hamdioui, and R. Bishnoi
    IEEE Design, Automation & Test in Europe Conference (DATE), 2025
  • [SPRN'25]
    Computation-In-Memory for Reliable and Energy-Efficient Diabetic Retinopathy Screening
    S. Diware, K. Chilakala, and R. Bishnoi
    Smart and Connected Health: AI, IoT, and Trustworthy Technologies, Springer Nature Switzerland, 2025
  • [ICCAD'25]
    Continuous On-Chip Learning in Neural Networks using SOT-MRAM based CIM Architectures
    A. Sehgal, S. Soni, S. Diware, A. K. Shukla, S. Roy, and R. Bishnoi
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2025
  • [DAC'25]
    Enhancing Parallelism and Energy-Efficiency in SOT-MRAM based CIM Architecture for On-Chip Learning
    A. Sehgal, A. K. Shukla, S. Diware, S. Soni, S. Dhull, S. Shreya, S. Roy, and R. Bishnoi
    ACM/IEEE Design Automation Conference (DAC), 2025
  • [ICCAD'24]
    Hardware-Aware Quantization for Accurate Memristor-Based Neural Networks
    S. Diware, M. A. Yaldagard, and R. Bishnoi
    IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2024
  • [TBCAS'23]
    Severity-Based Hierarchical ECG Classification Using Neural Networks
    S. Diware, S. Dash, A. Gebregiorgis, R. V. Joshi, C. Strydis, S. Hamdioui, and R. Bishnoi
    IEEE Transactions on Biomedical Circuits and Systems (TBioCAS), 2023
  • [AICAS'23]
    Mapping-Aware Biased Training for Accurate Memristor-Based Neural Networks
    S. Diware, A. Gebregiorgis, R. V. Joshi, S. Hamdioui, and R. Bishnoi
    IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2023
  • [TETCI'22]
    Accurate and Energy-Efficient Bit-Slicing for RRAM-Based Neural Networks
    S. Diware, A. Singh, A. Gebregiorgis, R. V. Joshi, S. Hamdioui, and R. Bishnoi
    IEEE Transactions on Emerging Topics in Computational Intelligence (TETCI), 2022

Courses

To be updated

Supervision

M.Sc. Alumni (TU Delft):
  • Manasi Diwate (2025)
  • Huixuan Wu (2025)
  • Siyuan Yu (2025)
  • Yingzhou Dong (2023)
  • Varun Sudhakar (2022)
  • Koteswararao Chilakala (2021)
  • Sudeshna Dash (2021)

Peer-Review

  • ACM/IEEE Design Automation Conference (DAC)
  • ACM/IEEE International Conference on Computer Aided Design (ICCAD)
  • IEEE Design, Automation & Test in Europe Conference (DATE)
  • IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
  • IEEE Transactions on Emerging Topics in Computational Intelligence (TETCI)
  • Springer Nature Biomedical Engineering Letters (BMEL)

Invited Talks

  • [2025]  MiM Webinar by Heidelberg University, Germany, "Hardware-Aware Quantization for Memristor-Based Neural Networks"
  • [2025]  Fraunhofer Institute for Integrated Circuits, Germany, "Hardware-Aware Quantization for Memristor-Based Neural Networks"
  • [2024]  IMEC Netherlands, "Computation-In-Memory for Edge-AI in Healthcare"
  • [2021]  GlobalFoundries visit to TU Delft, "Non-ideality Mitigation for Computation-In-Memory"
Some useful info before you read further:
  • My area is Hardware Design for AI, which is much different from Software AI and Data Science.
  • Hardware aspect of my work involves IC design and/or system-level behavioral simulations.
  • Literature related to both computation-in-memory basics and my research is available in the Research section.

Ph.D. Students

Who should reach out?

I am seeking motivated Ph.D. students with a strong background in VLSI circuit/system design and computer architecture.

Prior knowledge of deep learning and familiarity with PyTorch framework is a plus, but not mandatory.

What research directions are available?

An overview of the main research area and description of current research themes can be found in the Research section.

Students are free to extend these themes or even propose new ones, while remaining aligned with the main research area.

How to reach out?

Interested students are encouraged to email me with their CV throughout the year. Here is a typical example of an email template.

How to follow-up?

Please keep at least 4 working days between successive messages and do not expect responses on weekends.